Samar Singh Billawaria

Samar is an Associate Technical Director at Samsung India Research in Bengaluru, since July 2023. He leads SoC and IP design verification for multi-die, multi-CPU AI and mobile SoCs, including 2nm Exynos and memory programs. He sets the verification strategy and drives coverage closure to sign-off, aiming for first-pass silicon.

Samar leads a 27-engineer cross-functional team today, including vendor teams.

Nine SoCs. His career runs from 2004 to today, and the work covers verification strategy, coverage closure and tape-out sign-off through to production silicon.

Samar owns the India DV teams' verification for all custom HBM SoCs, covering HBM4, HBM4E and HBM5. He is responsible for SoC, IP and subsystem DV for internal and external customers, across the UCIe, D2D and DFI interfaces, CTPHY high-speed interconnect IP and the HBM memory-controller subsystem.

Samar brought LLM-agent workflows into the Samsung verification flow, with three results: verification planning for late IP additions is 70% faster, GLS bring-up is 50% faster, and coverage implementation for new customer requirements is 70% faster. He also enables the team's use of these LLM agents and trains them on best practices for using LLMs in co-development.

From September 2019 to May 2023 Samar led end-to-end verification of multi-CPU storage SoCs with RISC-V CPUs and UltraSoC RISC-V debug, across SD, SD Express, PCIe and SATA interfaces. He ran the full flow: verification planning, SoC simulation, FPGA-based verification, gate-level simulation, and post-tape-out tester-pattern delivery and debug.

Four: x86, ARM, RISC-V and ARC. His skills include assembly for all four.

At AMD, Samar verified the NorthBridge IP for AMD's first ARM-based client CPU, building ARM CPU BFM stimulus and UVM sequencers, checkers, monitors and scoreboards. He also ported the x86-only verification infrastructure to ARM, so legacy IP could be verified with ARM stimulus.

At Intel, as an individual contributor, Samar built the C++ toolchain for platform trace capture and emulation replay, used to reproduce post-silicon sightings on 8-, 10- and 15-core server processors. He also wrote the x86-assembly PSMI handler for microarchitectural state dumps, which became the tool of choice for sighting reproduction. He implemented automation of the silicon-emulation regression flow to 80% coverage of target test content, and sped up emulation by 7%.

Samar completed the IIT Delhi Advanced Robotics program in 2026 and received the Best Project Award. The project was a physical AI project: a robot hand with vision-language-action (VLA) model training.

Samar has managed consultant teams from multiple vendors end to end, from hiring and people management to vendor relations and approval of vendor purchase invoices, and has estimated and allocated program resources. At Sevitech Systems he owned project budgets, equipment purchasing and hiring, and wrote DV plans and resource estimates for complex new client SoCs.

Coverage-driven verification and closure, power-aware verification (UPF, PG-pin), gate-level simulation, FPGA prototyping, emulation (ZeBu), post-silicon debug and tester patterns, and C-based verification in which test cases are loaded into CPU memory and executed as firmware. He works in SystemVerilog and UVM, and also in OVM, Specman e and Vera.